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CMOS low noise amplifier design optimization technique

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5 Author(s)
Trung-Kien Nguyen ; Inf. & Commun. Univ., Daejeon, South Korea ; Nam-Jin Oh ; Hyung-Chul Choi ; Kuk-Ju Ihm
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In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3) for a power-constrained simultaneous noise and input matching low noise amplifier design optimization technique are introduced. Based on these expressions, the methodology to design LNA to archive the power-constrained simultaneous noise and input matching as well as satisfy the linearization condition is explained. In additional, the power gain is enhanced by using a very simple positive feedback. The proposed LNA for 5 GHz WLAN applications is fabricated based on 0.18 μm CMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and -5 dBm IIP3. The proposed LNA dissipates DC current of 3 mA at supply voltage of 2.5 V.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:1 )

Date of Conference:

25-28 July 2004