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Design techniques for CMOS very-low-voltage operational amplifiers with enhanced power supply rejection ratio

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3 Author(s)
Tsung-Sum Lee ; Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Wei-Chang Liu ; Chun-Teng Chung

Two very-low-voltage operational amplifiers in standard 0.35 μm CMOS process are presented. They have adopted folded-mirror active load and folded-cascode active load, respectively in the input stage, which save input swing. Cascode compensation offers a much improved high-frequency PSRR. Simulation results are provided and the corresponding performances are discussed and compared. Simulation results indicate that those circuits show superior power supply rejection at high frequencies.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:1 )

Date of Conference:

25-28 July 2004