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Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits

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2 Author(s)
A. E. Salama ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; M. I. Elmasry

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 6 )