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Test methodology for low power VLSI neural oscillator circuit

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6 Author(s)
Young Jun Lee ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Jihyun Lee ; Jaeyoung Heo ; Fengming Zhang
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This paper presents new test and verification methodologies, including design techniques targeting a neural oscillator. Because the output signal of a neuron is chaotic, customized verification and test methodologies are required. We have chosen to use MATLAB to verify our experimental results at a simulation level. In this paper we also describe a test circuit used to perform electronic neuron IC testing. We investigate how a subthreshold circuit can reduce power consumption. In our HSPICE simulations, we both validate the proposed test circuit and verify the electronic neuron and synapse circuit.

Published in:

Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE  (Volume:2 )

Date of Conference:

18-20 May 2004