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Hardware and software co-design in space compaction of cores-based digital circuits

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8 Author(s)
Assaf, M.H. ; Sch. of Inf. Technol. & Eng., Univ. of Ottawa, Ont., Canada ; Das, S.R. ; Petriu, E.M. ; Liwu Jin
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The implementation of a fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims at developing techniques in design verification and test architecture, utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embedded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design for testability. Specifically, applications of the built-in self-test (BIST) methodology in testing embedded cores are considered in the paper, with specific implementations being targeted towards ISCAS 85 combinational benchmark circuits.

Published in:

Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE  (Volume:2 )

Date of Conference:

18-20 May 2004

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