Cart (Loading....) | Create Account
Close category search window
 

Automated bus generation for multiprocessor SoC design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kyeong Keol Ryu ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Mooney, V.J.

The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global bus architecture (GBA) version I; 3) GBA version III; 4) hybrid bus architecture (Hybrid); and 5) split bus architecture. We verify and evaluate the performance of each bus system in the context of three applications: an orthogonal frequency division multiplexing wireless transmitter, an MPEG2 decoder, and a database example. Our methodology gives the designer a great benefit in the fast-design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types, and software programming style. In this paper, we show that BusSynth can generate buses that, when compared to a typical general GBA, achieve superior performance (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSynth is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:23 ,  Issue: 11 )

Date of Publication:

Nov. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.