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CAD for nanometer silicon design challenges and success

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1 Author(s)
Jeong-Taek Kong ; Samsung Electron. Co., Gyeonggi-Do, South Korea

As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complexity, and manufacturing-aware design techniques control the nanoscale physical effects. In this highlight paper, most nanometer design issues are described and the issues related to the higher level of abstraction are summarized. Process variability can be controlled by statistical design, resolution enhancement, planarity control, and other manufacturing-aware design techniques. Continuously growing problems such as leakage power, signal integrity, and reliability are also discussed. Finally, technology CAD for future nanometer devices is presented. For successful nanometer silicon design, closer cooperation among the design, process technology, mask, and CAD communities are essential.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:12 ,  Issue: 11 )

Date of Publication:

Nov. 2004

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