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Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

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6 Author(s)
Kiriyama, O. ; Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan ; Morimoto, T. ; Adachi, H. ; Harada, Y.
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We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 μm 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 × 31 pixels is 51.1mm2 and the integration density is 26.5pixel/mm2. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23μsec.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004