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A dynamically reconfigurable IP for data-intensive applications

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4 Author(s)
Miyamoto, N. ; Graduate Sch. of Eng., Tohoku Univ., Miyagi, Japan ; Karnan, L. ; Kotani, K. ; Ohmi, T.

In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004