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Comparative study of static and dynamic D-type flip-flop circuits using InP HBTs

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2 Author(s)
Hwan-Seok Yeo ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Jinwook Burm

A static and a dynamic D-type flip-flops (D-FFs) using InP heterojunction bipolar transistors (HBTs) were analyzed. Both the static and dynamic D-FFs employed conventional read/latch structure, however the dynamic D-FF had smaller latch current than the read current to improve the bandwidth. The static D-FF exhibited the maximum operating bit rate of 12 Gbit/s with rising/falling time of 67 ps/45 ps. The dynamic D-FF operated up to 20 Gbit/s with rising/falling time of 50 ps/32 ps. A dynamic D-FF exhibited the minimum operating bit rate of 1 Gbit/s.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004