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A 2.5Gbps serial-link data transceiver in a 0.35 μm digital CMOS technology

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2 Author(s)
Wei-Zen Chen ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan ; Meng-Chih Weng

This paper presents the design of a single chip serial link data transceiver. Incorporating with 8 to 1 multiplexer and 1 to 8 demultiplexer, the transceiving data rate ranges from 640 Mbps to 2.56 Gbps. In the transmitter side, a novel precharged type multiplexer is proposed to minimize deterministic jitter. In the receiver side, an oversampling data recovery loop utilizing mixed-signal phase picking scheme is adopted for data resynchronization and demultiplexing. A novel phase interpolator with resistive averaging technique is proposed to generate uniformly distributed sampling phases over wide frequency range, so as to improve bit error rate performance. For data packet size less than 1000 bytes, the tolerated frequency offset between transmitter and receiver is about 1.3 % by a built in elastic buffer. The measured data jitter at the transmitter side after multiplexing is 5.8 ps (rms), and is 43.3 ps (rms) at the receiver side after demultiplexing. The measured bit error rate for 2.5 Gbps data receiving is about 10-10. Fabricated in a 0.35 μm digital CMOS process, this chip occupies 2.9 mm × 2.4 mm. The total power consumption is 280 mW under 2V supply.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004