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Fast Fourier transform processor based on low-power and area-efficient algorithm

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2 Author(s)
Jung-yeol Oh ; Div. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Jeonju, South Korea ; Myoung-seob Lim

This paper proposes a new efficient FFT architecture with structured pipeline for OFDM systems, based on radix-24 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-22 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multiplier can enhance the area/power efficiency of the design. From synthesis simulations of a standard 0.35μm CMOS process, it achieved above 60% area reduction when compared with the conventional programmable multiplier.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004

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