Skip to Main Content
This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply-insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R & C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 μm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.