By Topic

A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hong-Yi Huang ; Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taiwan ; Jian-Hong Shen

In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and output frequency ranges of multiply-by-1/2/3/6 clock generator at 1.8V supply voltage are 138 MHz ∼ 277MHz and 138 MHz ∼ 1.6GHz, respectively.

Published in:

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Date of Conference:

4-5 Aug. 2004