Skip to Main Content
Summary form only given. The integrated circuit manufacturing process has inevitable imperfections and fluctuations that result in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated. The impact of such variations on various aspects of chip performance has been the subject of numerous papers, and techniques for analyzing and dealing with such variability, broadly labelled design for manufacturability, are emerging as the next hot topic in this area. The focus of much of the current work in this area has been on timing, but it is well known that modern integrated circuits are very heavily power limited and that static and dynamic power have emerged as first class design objectives. In this paper, we review the various sources of process variability, and relate them to variability in the various parts of the power delivery subsystem. Specifically, we address variability in the following areas: 1. static (leakage) power; 2. dynamic power; 3. on-chip power grid; 4. on-chip decoupling capacitance; 5. package power grid; 6. workload. It is important to model all these sources of variability with the correct balance of effort and accuracy, thus it is important to get broad bounds on each of the sources in order to insure that the appropriate level of modeling and analysis investment is made in order to bound or worst-case each component without undue pessimism. It is also important to have a first order understanding of the technology trends in each of these sources of variability. This will allow the designer and CAD tool developer to anticipate future problem areas and plan work arounds as needed.