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Low-power carry-select adder using adaptive supply voltage based on input vector patterns

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3 Author(s)
Suzuki, H. ; Renesas Technol. Corp., Hyogo, Japan ; Jeong, W. ; Roy, K.

Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose adaptive supply voltage carry-select adder (CSA) based on the input vector patterns. A proposed level converter based on the complementary pass transistor logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004

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