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A CPL-based dual supply 32-bit ALU for sub 180 nm CMOS technologies

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3 Author(s)
B. Chatterjee ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; M. Sachdev ; R. Krishnamurthy

In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180 nm-65 nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004