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Post-layout leakage power minimization based on distributed sleep transistor insertion

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4 Author(s)
Babighian, P. ; Politecnico di Torino, Italy ; Benini, L. ; Macii, A. ; Macii, E.

This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysts on several benchmarks placed and routed with state-of-the art commercial tools for physical design.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004