By Topic

Improved clock-gating through transparent pipelining

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Jacobson, H.M. ; IBM T.J. Watson Res. Center, Yorktown, NY, USA

This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 40-60% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004