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Experimental measurement of a novel power gating structure with intermediate power saving mode

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4 Author(s)
Suhwan Kim ; Dept. of Electr. Eng., Seoul Nat. Univ., South Korea ; Kosonocky, S.V. ; Knebel, D.R. ; Stawiasz, K.

A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 μm CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004