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Technology exploration for adaptive power and frequency scaling in 90nm CMOS

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3 Author(s)
Meijer, M. ; Philips Res. Labs., Eindhoven, Netherlands ; Pessolano, F. ; de Gyvez, J.P.

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modem deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8× power savings by 3.4× frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22× power savings with 5× frequency downscaling by combining AVS and ABB, as well as 22× leakage reduction.

Published in:

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Date of Conference:

9-11 Aug. 2004

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