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On undetectable faults in partial scan circuits using transparent-scan

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2 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Reddy, S.M.

We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive test compaction compared to other approaches. We demonstrate that, unlike other approaches that provide high levels of test compaction for partial scan circuits, this approach does not increase the number of undetectable faults. We also discuss the monotonicity of the number of undetectable faults with increased levels of scan.

Published in:

Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on

Date of Conference:

11-13 Oct. 2004