By Topic

Reliable system co-design: the FIR case study

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
C. Bolchini ; Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy ; A. Miele ; F. Salice ; D. Sciuto
more authors

This paper proposes a digital design methodology aiming at introducing certain degrees of reliability in case of hardware failures. Three main differences with respect to the traditional design methodologies for reliability are introduced: first, the peculiarities of the specification language are taken into account by exploiting the features of SystemC to introduce fault detection properties; second, different techniques are considered to determine the best cost/performance trade-off; third, the adoption of the desired reliability properties is carried out transparently to the designer. The three aspects together characterize the proposed approach, presented here through its application to a FIR circuit.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

Date of Conference:

10-13 Oct. 2004