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Non-intrusive test compression for SOC using embedded FPGA core

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2 Author(s)
Zeng, G. ; Graduate Sch. of Sci. & Technol., Chiba Univ., Japan ; Ito, H.

In this paper, a complete non-intrusive test compression solution is proposed for system-on-a-chip (SOC) using embedded FPGA core. The solution achieves low-cost testing by employing not only selective Huffman vertical coding (SHVC) for test stimuli compression, but also MISR-based time compactor for test responses compaction. Moreover, the solution is non-intrusive, since it can tolerate any number of unknown states in output responses such that it does not require modifying the logic of core to eliminate or block the sources of unknown states. Furthermore, the solution obtains improved diagnostic capability over conventional MISR by combining masking logic with a modified MISR. Experimental results for ISCAS 89 benchmarks as well as a platform FPGA chip have proven the efficiency of the proposed test solution.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

Date of Conference:

10-13 Oct. 2004