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The noise immunity of modern CMOS digital design has become an important metric, as well as its power consumption. In this paper, we evaluate the noise immunity of static CMOS low power design schemes in terms of logic and delay error. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron is presented. Then the model is applied to the most well known low power design schemes to find the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance could be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 μm CMOS technology.