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A VLSI architecture of JPEG2000 encoder

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6 Author(s)
Liu, Leibo ; Inst. of Microelectron., Tsinghua Univ., China ; Ning Chen ; Hongying Meng ; Li Zhang
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This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 11 )

Date of Publication:

Nov. 2004

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