Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Next generation packaging technology for high performance ASICs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Brillhart, M. ; Cisco Syst. Inc., San Jose, CA, USA ; Jie Xue

As the data rate of high performance Internet router systems continues to increase, meeting the challenges for high speed electrical performance drives ASIC packaging technology to higher silicon integration, higher I/O density, and enhanced thermal power dissipation. The requirement of high Si integration with the increasing needs for embedded SRAM and DRAM drives for the increase in Si die size and the demand for 90nm technology. Die size up to 20×20 mm is pushing advanced packaging substrate technology. High I/O density also drives the needs for finer bump pitch and larger package body size, which present challenges for package and card level assembly. Moreover, high availability telecommunication products demand excellent reliability not only at the ASIC package and card assembly level, but also at the final product system level.

Published in:

High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on

Date of Conference:

30 June-3 July 2004