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A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

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8 Author(s)
Tsuji, T. ; MCU&SOC Bus. Unit, Renesas Technol. Corp., Itami, Japan ; Tanizaki, H. ; Ishikawa, M. ; Otani, J.
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A 1Mbit MRAM with a 0.81 μm2 1-Transistor 1-Magnetic Tunnel Junction (1Tr-1MTJ) cell using 0.13 μm 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n+ diffusion/Co-silicide read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

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