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CMOS transceiver with baud rate clock recovery for optical interconnects

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4 Author(s)
Emami-Neyestanak, A. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Palermo, S. ; Hae-Chang Lee ; Horowitz, M.

An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 μm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004