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A quad multi-speed serializer/deserializer with analog adaptive equalization

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12 Author(s)
Hui Wang ; Broadcom Corp., Irvine, CA, USA ; Xicheng Jiang ; Tam, D. ; Cheung, F.
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A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25μm CMOS technology is described. It uses a 4× interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 231-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

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