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Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm

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4 Author(s)
Mukaida, K. ; Fujitsu Ltd., Kanagawa, Japan ; Takenaka, M. ; Torii, N. ; Masui, S.

High-speed and area-efficient Montgomery modular multipliers for RSA algorithm has been developed for digital signature and user authentication in high-speed network and smart card systems. Multiplier-accumulator (MAC) in the developed Montgomery modular multiplier has non-identical multiplicand/multiplier word length. This organization eliminates the bottleneck in memory bandwidth, and enables to use single-port memory for area and power reductions. The developed MAC is faster than the common word length organization due to short critical path. 5,000 digital signature productions/sec is obtained with a three-stage pipelined architecture in 0.18 μm CMOS technology.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

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