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A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

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7 Author(s)
Pilo, H. ; IBM Microeletronics Div., Essex Junction, VT, USA ; Braceras, G. ; Hall, S. ; Lamphier, S.
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This paper describes a 36Mb SRAM with an internal random cycle of 0.9ns and is capable of driving and receiving data at 1.1Gb/s/pin on input and output pins simultaneously. The 115mm2 die is fabricated in a 0.13 μm process. High-VT array devices are used to reduce array sub-threshold leakage by 22×. The SRAM features include an improved architecture that segments the 36Mb array into six equal 6Mb sextants. Each sextant supports 1/6th of the 36b I/O width. All sextants of the array are equally timed to reduce the fastest-to-slowest access skew from the previous architecture. Separate input and output pins provide concurrent read and write operations for two random addresses per cycle. The cycle-time is achieved using the improved architecture and a self-timed read to write (STRW) protocol. The STRW protocol improves cycle time by over 20%.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004