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We report a wide band low jitter PLL implemented in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. Using the thick and thin gate dielectric/oxide options available, two separate PLL designs are implemented. At a 1.5 V supply, the maximum operating frequency of the PLL is 13.9 GHz and 7.5 GHz for the thin and thick gate oxide designs, respectively. At a 1.5 V supply, with a feedback divide ratio of 8, cycle-to-cycle (C-C) jitter was measured at 14.2 ps P-P/2.1 ps RMS and 11.1 ps P-P/1.6 ps RMS for the thin and thick oxide designs, respectively. At 2.1 V the maximum operating frequency of the thin oxide PLL is 17.3 GHz and at 16 GHz has 8.9 ps P-P/1.2 ps RMS C-C jitter, while the maximum frequency for the thick oxide PILL is 10.4 GHz. To our knowledge, these results show the highest frequency to date of any CMOS PLL and the lowest jitter of any known wide band CMOS PLL.
Date of Conference: 17-19 June 2004