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A circuit design based approach for 1/f-noise reduction in linear analog CMOS IC's

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4 Author(s)
J. Koh ; Corporate Res., Infineon Technol. AG, Munich, Germany ; R. Thewes ; D. Schmitt-Landsiedel ; R. Brederlow

A new circuit design based approach for 1/f noise reduction in linear analog CMOS circuits is presented using a device physics based effect. Compared to a reference circuit, a threefold reduction (5 dB) at 10 Hz in 1/f noise is achieved for an operational amplifier designed in a standard 0.12 μm, 1.5 V CMOS technology.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004