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Gabor filtering is a powerful feature extraction method for image recognition. We propose a pixel-parallel processor for Gabor filtering using a newly developed algorithm with nearest-neighbor connections. The LSI has been designed using 0.35 μm CMOS technology based on the merged analog/digital circuit architecture, which uses pulse-width modulation (PWM) signals. The LSI includes 62×71 pixel circuits on a 9.8 mm sq. chip area. Experiments using the fabricated LSI have verified that the spatial frequency of the image is correctly extracted.