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A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-μm cost-effective DRAM technology

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9 Author(s)
Noda, H. ; Elpida Memory, Inc., Kanagawa, Japan ; Miyatake, S. ; Sekiguchi, T. ; Takemura, R.
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A 144-Mb twin-cell-memory was fabricated using 0.11-μm cost-effective DRAM technology. A direct-sense-amp with a three-stage sensing scheme can achieve a random access time of 4.8 ns. The source-separated restore-sense-amp enables a random cycle time of 6.0 ns. The peak bandwidth is 48 Gb/s with separate I/O and simultaneous read/write operations. High performance was also realized using W/WNx dual-gate CMOS technology with a p+ gate memory-cell-transistor.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004