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SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation

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7 Author(s)
Blagojevic, M. ; Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland ; Pastre, M. ; Kayal, M. ; Fazan, P.
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Recently, the new concept of the capacitor-less 1T DRAM cell has been developed. The memory cell (MC) using a single transistor on SOI exploits the Floating Body (FB) effect of partially depleted (PD) SOI devices. The memory state can be read through the drain current of the storage transistors, i.e. I0 and I1 respectively. To read the information stored in a 1T DRAM cell, the current of the selected MC is compared to Iref . In this paper, we propose a sensing method with automatic reference generation for SOI capacitor-less 1T DRAM. An adjustable current source is implemented as reference current source in order to sense the MC state. A digital-to-analog converter (DAC) and a successive approximation algorithm perform the calibration of Iref.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004