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A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit

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6 Author(s)
Bruels, N. ; Corporate Res., Infineon Technol.,, Munich, Germany ; Sicheneder, E. ; Loew, M. ; Schackow, A.
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A 0.13 μm CMOS add-compare-select unit (ACSU) is presented allowing for a maximum data rate of 2.8 Gb/s. A modified bit-level pipelining scheme combined with a new state metric representation has been implemented using single-rail DOMINO logic and static CMOS gates. The adaptation of architecture and circuit technique results in a compact energy-efficient design. The 0.5mm2 chip consumes 970mW at 2 Gb/s (VDD = 1.2 V) and 2.2 W at 2.8 Gb/s (VDD = 1.5 V).

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004