Skip to Main Content
A CMOS 64MSps 2-1-1 cascaded ΣΔ I/Q modulator optimized for WCDMA applications achieves more than 13 bits over 2MHz bandwidth. A new way for sizing cascaded ΣΔ architectures based on comparator equivalent gain, and an improved dynamic element matching method resulted into an area and power efficient modulator design. The total consumption of two modulators plus built-in voltage and current reference generators is about 20mA at 2.7V. Total active area is 0.85mm2 in a 0.35 μm CMOS technology.
Date of Conference: 17-19 June 2004