Cart (Loading....) | Create Account
Close category search window
 

Power analysis for high-speed I/O transmitters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hatamkhani, H. ; California Univ., Los Angeles, CA, USA ; Yang, C.-K.K.

This paper studies the design tradeoffs to minimize power dissipation of multi-Gbps parallel I/O transmitters. A macromodel of a transmitter that can be optimized for power is presented. Also discussed is a means to consider the impact of deterministic jitter due to on-chip buffering on power dissipation. The model allows analysis that considers varying design constraints, and circuit architectures. The optimization results provide some guidance on the choice of architecture, and data rate to achieve large aggregate I/O bandwidths.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.