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A quad transceiver cell is designed and implemented in 90nm CMOS technology with a 1V nominal supply. To minimize area and power consumption, the cell uses a single dual-loop PLL. Gate-current leakage compensator is used to mitigate gate-current leakage in the PLL loop-filter capacitor. The quad cell consumes 73mW/link at 3.125Gbps with 500mV output swing driving double-terminated links and achieves a peak-to-peak transmit jitter of 42ps at 4Gbps data rate.
Date of Conference: 17-19 June 2004