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A 3.3-V 240-MS/s CMOS bandpass ΣΔ modulator using a fast-settling double-sampling SC filter

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2 Author(s)
V. S. L. Cheung ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; H. C. Luong

A bandpass ΣΔ modulator is demonstrated to operate at a very high sampling rate of 240 MS/s by employing a proposed double-sampling switched-capacitor biquadratic filter architecture, which processes with a fast-settling feature. Implemented in a standard 0.35-μm CMOS process, the modulator achieves a peak SNDR of 72 dB, 55 dB and 52 dB at a bandwidth of 200 kHz, 1 MHz and 1.25 MHz for GSM, Bluetooth and CDMA2000 applications respectively while dissipating 37 mW and occupying a chip area of 1.2 mm2.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004