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A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13 μm CMOS

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5 Author(s)
Hee-Cheol Choi ; Samsung Electron. Co. Ltd., Yongin, South Korea ; Seung-Bin You ; Ho-Young Lee ; Ho-Jin Park
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A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm2 is implemented in a 0.13 μm CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of ±0.90 LSB and ±6.1 LSB, respectively.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004