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A Σ-Δ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

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6 Author(s)
In Chul Hwang ; Syst. LSI Div., Samsung Electron. Co. Ltd., Yongin, South Korea ; Han-Il Lee ; Kun-Seok Lee ; Je-Kwang Cho
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This paper presents a fractional-N synthesizer with a 3-bit 4th-order interpolative Σ-Δ modulator for a GSM/GPRS direct conversion transceiver. With an integrated VCO and an integrated loop filter, the synthesizer achieves the phase noise performances less than -78dBc/Hz at close-in offset and less than -116dBc/Hz at 400kHz offset. The chip was fabricated and evaluated in a 0.35 μm SiGe BiCMOS process.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004