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An efficient interconnect capacitance extractor using a blocked equation solving technique

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3 Author(s)
Hong Liu ; Dept. Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Wenjian Yu ; Zeyi Wang

With the development of the VLSI process technology, the electrical parameters of interconnects are becoming more and more important factors dominating the circuit performance. This raises the requirement to calculate the parasitic parameters even more quickly and accurately. This paper presents a blocked equation solving technique, implemented in a two-dimensional (2D) parasitic capacitance extractor using the direct boundary element method. Numerical experiments show that the blocked equation solution is superior to the GMRES iterative solver. And for the typical interconnect structure of parallel lines with copper technology, our method consumes much less CPU time and memory, compared with the famous commercial software Raphael.

Published in:

Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on  (Volume:2 )

Date of Conference:

27-29 June 2004