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Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

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30 Author(s)
V. Arnal ; STMicroelectronics, Crolles, France ; R. J. O. M. Hoofman ; M. Assous ; P. H. L. Bancken
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Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.

Published in:

Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International

Date of Conference:

7-9 June 2004