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In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFETs, for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the ID degradation is due to the channel length shortening, and the electron trap is dominant for the device degradation. While for thin gate oxide, the ID degradation is due to width narrowing, and the hole trap is dominant, in which both electron and hole trap induced VT shifts are significant. The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔVT in thin-oxide with reduced width.