By Topic

Applications of plan-view TEM analysis to IC debugging

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Hsieh, Y.F. ; Mater. Anal. Technol. Inc., Hsin-Chu, Taiwan ; Chen, J.C. ; Lo, C.K. ; Wu, Y.R.
more authors

In this report, applications of plan-view TEM analyses to IC debugging has been applied to some FA cases, where frequently used tools, such as SEM, FIB, AFM, etc., are not able to reveal the crystalline defects buried in the Si substrate. The novel examples include IC process induced oxidation stacking faults, sidewall profile of shallow trench isolation (STI), aggressive layout design induced active-to-active area breakdown, mask design error induced improper ion implantation, ESD failure induced local bum-out, and metal silicide encroachment.

Published in:

Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the

Date of Conference:

5-8 July 2004