Technology and reliability challenges - a foundry perspective [semiconductor foundry]

Many technology and reliability challenges emerge as we continue to push Moore's Law. On the lithography front, ArF 193 nm liquid-immersion lithography offers great promise to provide us with cost-effective manufacturing solutions to the 32 nm generation. Transistor and interconnect scaling require new materials and structures that may not be conventional in the nanometer regime, e.g., strained-Si channel, high-/spl kappa/ gate dielectric, metal gate, non-bulk or non-planar CMOS structures, low-/spl kappa/ interconnects, and many SoC-enabling features. The foundry is in a unique position to work with the rest of the industry to overcome these challenges and provide cost-effective solutions in a collaborative and virtually integrated way. New methodology, infrastructure, circuit design, and system architecture solutions are needed for all phases and aspects of the technology development, qualification, and manufacturing, e.g., modeling, characterization, failure analysis, concurrent process and reliability engineering, design for manufacturing, and design for test/debug.