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SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

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14 Author(s)
Tamura, Y. ; Semicond. Leading Edge Technol., Inc., Ibaraki, Japan ; Sasaki, T. ; Izumi, N. ; Ootsuka, F.
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This paper describes the SiN-capped HfSiON gate stacks for 65 nm-node low-standby-power transistors with improved bias temperature instabilities (BTI). By employing SiN-cap on HfSiON and the counter-implant for adjustment of pFET's threshold voltage (VTH), the symmetrical VTH values for nFETs and pFETs have been obtained. The nitrogen incorporation in the interfacial oxide prevents the interface states generation under positive bias temperature stress. Negative BTI can be improved by reducing the thickness of SiN-cap. 10-year lifetimes for both positive and negative BTI have been achieved.

Published in:

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

15-17 June 2004